Métodos para reducir ruido en señales mixtas-ASICs

            (EOL/Oswaldo Barajas).- Si de señales mixtas se trata en el desarrollo de Circuitos Integrados para Aplicaciones Específicas (ASIC, por sus siglas en inglés) el conocimiento sobre los actuales sistemas de simulación de ruido, características de los mismos sensores y su debida cualidad de interface sensorial, serán los mejores aliados para el ingeniero diseñador a fin de que logre consolidar un proyecto exitoso en términos de desempeño y reducción de ruido.

            Este artículo vierte algunas sugerencias halladas en el caso de estudio realizado por el ingeniero francés Thierry Masson, experto por más de 23 años en el campo de señales mixtas con ASICs y interfaces sensoriales para las industrias automotriz, industrial y médico, siendo parte fundamental en el campo de desarrollo para la compañía en la cual laboró "e2v".

            Tomando como referencia el documento sobre convertidores de datos Delta-Sigma, publicado en el año 1996 por los investigadores Steven R. Richard y Gabor C. Temes de la compañía John Wiley & Sons Inc., se indica que los ingenieros asociados al diseño de sistemas de señales mixtas con ASIC, deben recurrir al mejor método de desarrollo, además de emplear técnicas adecuadas de modelado para cada sub-bloque en cada de uno de los niveles para conocer ampliamente los requerimientos del sistema.

            Para lograr niveles bajos de ruido, los desarrolladores deben examinar los modelos de suministros. Además es común la utilización por parte del grupo de diseñadores de propiedad intelectual en cada uno los pasos de la etapa de desarrollo, por lo que antes de conseguir patentes, es necesario un amplio conocimiento en las herramientas de simulación existentes actualmente en el mercado. En este mismo aspecto, hay proyectos en donde se requieren de convertidores de datos (Sigma-Delta), amplificadores de bajo ruido y referencias de voltaje estable, por mencionar algunos, que en conjunto serán parte esencial para llegar al objetivo.

Fuentes de ruido

            El criterio del ruido de salida de la cadena de medición es un factor importante, pues determinará la resolución final. El documento de Thierry Masson señala que las fuentes del ruido de salida provienen tanto de la cuantización del ADC y del ruido térmico de la electrónica, incluyendo el sensor. El ruido dependerá de los coeficientes de transferencia del modulador Delta-Sigma ytambién de la cantidad de post-filtrado que el sistema de conversión decimal provea. Entre tanto, el radio de coeficiente de sobre-muestreo debe ser solucionado desde los 128 a 1024. Este aspecto también dependerá directamente del propio elemento sensorial en el caso de que no sean solucionados los coeficientes de función de transferencia.


Un amplificador operacional es una gran fuente de ruido térmico.

            En cuanto al ruido térmico, éste aparecen en el primer nivel al interior del modulador, mientras que las principales fuentes son manipuladas y el Amplificador Operacional (Op-Amp). Se indica que mientras que el convertidor Delta-Sigma trabaja con técnicas especializadas en datos de muestra, las frecuencias originadas promueven el ruido alrededor de las mismas en el mismo sistema, para lo cual entra en acción el modulador. La transformación o conversión del ruido térmico pasa a ser entonces un clásico kT/C, donde k es la constante de Boltzmann, T es la temperatura y C la capacitancia. En el caso del Op-Amp, también se recogen ruidos térmicos sobre las frecuencias, sin embargo se entiende que dependerá en demasía del elemento de sensado tal como se muestra en la siguiente ilustración.  

Fuente: http://electronicosonline.com/noticias/notas.php?id=A5307_0_1_0_C&page=8214

Fuente: http://ewh.ieee.org/reg/9/etrans/ieee/issues/vol3/vol3issue3July2005/3TLA3_02Linares.pdf

  

Las aplicaciones emergentes conducen los avances en los amplificadores

Mejoras en los niveles de ruido

      Pero el orden establecido está cambiando; las exigencias cada vez mayores de un funcionamiento de bajo ruido en el diseño de los apara­tos electrónicos de uso general está forzando la aparición de nuevas ge­neraciones de circuitos integrados para amplificadores de bajo ruido que ofrecen mejor rendimiento ge­neral. Históricamente, la creación de un amplificador de bajo ruido ha­cía necesario que los diseñadores de circuitos integrados intercambiaran otros aspectos del funcionamiento como la velocidad, la corriente de polarización de entrada y el consumo de la energía. El tamaño del dado y de la cápsula de los dispositivos de bajo ruido tienden también a ser mayores que los de los amplificadores de uso general. En las aplicaciones de bajo ruido tradicionales, como en las comunicaciones por satélite, radar o GSM inalámbrico, tales inconvenien­cias han sido secundarias a la impor­tancia de obtener el rendimiento de ruido requerido. Sin embargo, con las realidades comerciales modernas fre­cuentes en las últimas generaciones de aplicaciones de bajo ruido, surgen requisitos necesarios de bajo ruido de tensión y de bajo ruido de corriente, además de baja energía, precio eco­nómico y pequeño tamaño.

Otras exigencias importantes que afectan a los sistemas modernos in­cluyen el soporte de la oscilación de la tensión de entrada o salida de un carril a otro, para potenciar al máxi­mo el rango dinámico de la señal ya que los amplificadores deben operar a partir de unas tensiones de alimen­tación del sistema progresivamente inferiores. Otros requisitos incluyen el rechazo de la alimentación de alta potencia, por ejemplo en los produc­tos diseñados para operar a partir de una tensión de batería no regulada. Estos deben también operar sobre la gama total de tensión útil de la batería, ya que la tensión de alimen­tación decae progresivamente del nivel totalmente cargado. Satisfacer todos estos requisitos en un solo am­plificador es un reto.

Las innovaciones del proceso en las tecnologías bipolar, JFET y CMOS han posibilitado nuevas familias de dispositivos que muestran propieda­des muy optimizadas. Un ejemplo:  ­­­­los amplificadores bipolares líderes están adoptando una nueva tecnología de aislamiento por zanja en lugar de la estructura tradicional de capa de difusión para obtener una densidad de transistor mayor por dado. Esta tecnología ofrece mayor velocidad, adaptación, linealidad y estabilidad, además de reducir el ruido producido por la tensión y la corriente. Los beneficios incluyen menor consumo de energía, operar sobre una gama extendida de temperaturas sin que se requieran disipadores térmicos, y que los encapsualdos sean más pequeños, con lo cual se pueden obtener densidades mayores en los diseños de canal múltiple.

            Los avances en la tecnología de fabricación JFET incluyen la cons­trucción de transistores multipuer­ta para el rendimiento óptimo por área de transistor, lo cual ha permi­tido reducir el ruido de la tensión manteniendo simultaneamente un ruido de corriente ultra bajo. Con un ruido de tensión en el rango de 4-6nV/√Hz y un ruido de corriente de menos de 1fA/√Hz, los disposi­tivos de la última generación han obtenido un ruido total bajo sobre una amplia gama de impedancia de transductor. Presentan una solución especialmente robusta cuando se tratan de amplificar señales de bajo nivel procedentes de generadores de impedancia alta, especialmente de transductores capacitivos, como los hidrófonos, los acelerómetros de precisión o los fotodiodos.

            El desarrollo del amplificador CMOS se está también enfocando en los avances en el nivel de silicio para eliminar los compromisos entre aspectos tales como baja derivación y bajo ruido, que también han sido difíciles de combinar en un sólo dis­positivo. Otros avances de procesos incluyen el silicio con aislador (SOI) BiCMOS, que ofrece una precisión mejorada de CC, un bajo consumo de la energía y bajo ruido de tensión. Diseñados para tensiones de alimen­tación de 0,9V-12V, que incluye la optimización para una operación de 3,3V-5V, permiten la interconexión directa al convertidor A/D además de la compatibilidad con la química de la batería, como las de ión de Li, ha­ciendo que sean muy adecuados para utilizar en los dispositivos portátiles.

Fuente: http://www.redeweb.com/_txt/641/60.pdf

Los analizadores de espectro serie 3280 ofrecen ahora demodulación  digital para análisis de redes inalámbricas

            La serie 3280 resulta ideal para pruebas en ingeniería de radio tanto en diseño, como en investigación y desarrollo y producción. La serie Aeroflex 3280 de analizadores de espectro ofrece ahora demodulación digital para análisis de redes inalámbricas 802.11a, b y g. La demodulación digital de los 3280 permite analizar las características de transmisión de los dispositivos inalámbricos.

           

            La demodulación digital de la serie 3280 resulta fácil de manejar en sus dos modos. El modo Full-frequency conecta la salida IF de 421.4 MHz del panel posterior con la entrada del demodulador, con lo que el usuario demodula señales en todo el ancho de banda del analizador de espectro (3 GHz, 13.2 GHz o 26.5 GHz). El modo Dual-channel conecta directamente al panel frontal del equipo o, de forma opcional, a través de un conector del panel posterior, para crear un instrumento real de dos canales. El rango de frecuencias para entrada directa del demodulador es de 300MHz a 3GHz. Aunque la opción de demodulación digital de la serie 3280 no incluye salida directa de I y Q, el usuario que lo precise tiene acceso a una salida digital serie I&Q a través de un cable LVDS opcional (Low- Voltage Data Signal). Este cable opcional

se coloca internamente entre la salida LVDS del demodulador y el panel posterior del analizador de espectro. La serie 3280 de analizadores de espectro de 3 Hz a 26.5 GHz son conocidos por ofrecer muchas más prestaciones que las esperadas para su gama – ofreciendo impresionantes especificaciones en RF y microondas, conectividad excepcional y muchas otras prestaciones fáciles de usar a un precio asequible. La serie 3280 cuenta con un alto nivel de precisión, ±0.15 dB hasta 3 GHz. Otras prestaciones a resaltar son su Oscilador local de bajo ruido de fase, <-115 dBm/ Hz, 1GHz/ 10 kHz offset y producto de intermodulación de tercer orden de +18

dBm. La FI digital ofrece anchos de banda de resolución de 5 MHz a 1 Hz. El sistema operativo Windows® XP, el disco duro interno y su CD-ROM hacen de la serie 3280 una herramienta muy fácil de utilizar permitiendo un amplio rango de interfaces, incluyendo acceso a LAN, USB, RS-232, IEEE 488 (GPIB) y salida VGA, el puerto paralelo Centronics permite su conexión a impresora, y cuenta con conexiones para ratón y teclado. La serie 3280 cuenta con una gran pantalla TFT de 10.4 pulgadas con una amplia zona de visión, con lo que los datos

demuestran con gran visibilidad incluso con pantalla compartida y elevada luminosidad ambiente. Se pueden mostrar hasta tres trazas simultáneamente por ventana y hasta nueve marcadores, con posibilidad de abrir una ventana adicional con el listado de los marcadores.

Las funciones ya implementadas simplificarán las tareas más comunes a las que se destine el 3280, entre ellas: potencia decanal, potencia en canal adyacente, banda ocupada, máscara de espectro, medida de TOI, distorsión armónica, ancho de banda a X dB, medida de ruido de fase.

Fuente: http://www.redeweb.com/_txt/631/46.pdf

Avances en los circuitos integrados

            Los avances que hicieron posible el circuito integrado han sido, fundamentalmente, los desarrollos en la fabricación de dispositivos semiconductores a mediados del siglo XX y los descubrimientos experimentales que mostraron que estos dispositivos podían reemplazar las funciones de las válvulas o tubos de vacío, que se volvieron rápidamente obsoletos al no poder competir con el pequeño tamaño, el consumo de energía moderado, los tiempos de conmutación mínimos, la confiabilidad, la capacidad de producción en masa y la versatilidad de los CI.

            Entre los circuitos integrados más avanzados se encuentran los microprocesadores, que controlan todo desde computadoras hasta teléfonos móviles y hornos microondas. Los chips de memorias digitales son otra familia de circuitos integrados que son de importancia crucial para la moderna sociedad de la información. Mientras que el costo de diseñar y desarrollar un circuito integrado complejo es bastante alto, cuando se reparte entre millones de unidades de producción el costo individual de los CIs por lo general se reduce al mínimo. La eficiencia de los CI es alta debido a que el pequeño tamaño de los chips permite cortas conexiones que posibilitan la utilización de lógica de bajo consumo (como es el caso de CMOS) en altas velocidades de conmutación.

            Con el transcurso de los años, los CI están constantemente migrando a tamaños más pequeños con mejores características, permitiendo que mayor cantidad de circuitos sean empaquetados en cada chip (véase la ley de Moore). Al mismo tiempo que el tamaño se comprime, prácticamente todo se mejora (el costo y el consumo de energía disminuyen a la vez que aumenta la velocidad). Aunque estas ganancias son aparentemente para el usuario final, existe una feroz competencia entre los fabricantes para utilizar geometrías cada vez más delgadas. Este proceso, y el esperado proceso en los próximos años, está muy bien descrito por la International Technology Roadmap for Semiconductors, o ITRS.

Fuente: http://es.wikipedia.org/wiki/Circuito_integrado#V.C3.A9ase_tambi.C3.A9n

Bre siOn Circuit Techniques to Improve Noise Immunity

of CMOS Dynamic Logic

For ease of presentation, in this paper our discussion will be focused on one type of dynamic circuits known as domino CMOS logic circuits [3], which is probably the most widely used dynamic logic style. However, it is noted that the noisetolerant design techniques discussed in this paper can also be applied to other types of dynamic circuits. A typical n-type domino CMOS logic gate, as shown in Fig. (a),  onsists of clock controlled transistors M1 and M2, a pull-down n-type transistor network, and an output driver.  He operation of a domino CMOS logic gate can be divided into two phases. In the precharge phase when the clock CK is low, the dynamic node S is charged to logic high through M1 and the output of the gate Q is low. The evaluation phase starts when the clock goes high. In this phase, M1 is OFF and M2 is ON. The dynamic node S discharges or retains its charge depending on the inputs to the pull-down network. An example 2-input domino AND gate is illustrated in Fig. (b). Noise sources in dynamic logic circuits can be broadly classified into two basic types: i) gate internal noises, including charge sharing noise, leakage noise, and so on and ii) external noises, including input noise, power and ground noise, and substrate noise.

1)       Charge sharing noise is caused by charge redistribution between the dynamic node and the internal nodes of the pull-down network. Charge sharing reduces the voltage level at the dynamic node causing potential false switching of a dynamic logic gate.

2)       Leakage noise refers to the possible charge loss in the evaluation phase due to subthreshold leakage current. Leakage current increases exponentially with respect to transistor threshold voltage, which is continuously being down-scaled as the power-supply voltage reduces. Therefore, leakage in transistors can be a significant source of noise in wide dynamic logic gates designed using very deep submicron process technology.

3)       Input noise refers to noise presented at the inputs of a logic gate. They are primarily caused by the coupling effect, also known as crosstalk, among adjacent signal wires. This type of noise has become a prominent source of failures for deep submicron VLSI circuits because of the aggressive interconnect scaling in the lateral dimensions with relatively unchanged vertical dimensions.

The simple feedback keeper technique is effective against noises and is easy to design. However, there is a fundamental dilemma in choosing the size of the keeper. On one hand, a strong keeper is required to achieve high gate noise tolerance. On the other hand, large keeper leads to significant contention during normal gate switching, therefore deteriorates gate performance. The conditional keeper techniques  temporarily disable the keeper or reduce keeper strength to alleviate the contention problem. But dynamic gates equipped with those keepers are susceptible to input noise glitches because the dynamic node is not adequately protected during the gate switching time window. Noise immunity against input noises is very difficult to achieve without significant sacrifice in circuit performance because the gate should not act before it identifies whether the input is noise or real signal. This inevitable time needed to distinguish noise from real signal, which is obtained by monitoring the initial period of the input voltage waveform, causes degradation in circuit performance. The performance overhead due to the additional circuitry that helps improve input noise immunity cannot be completely eliminated. However, it can be reduced to a large extent. In this paper, we propose a new technique that enhances dynamic gate noise immunity against all types of noises including the input noise. The proposed technique incurs very little cost in performance.

NOISE MARGIN AND DELAY ANALYSIS

                In this section, we analytically study the noise margin as well as the discharge time of domino logic gates with the proposed NDR keepers. For simplicity of analysis, we assume the – characteristic of the NDR keeper can be modeled using a piecewise linear waveform as shown in Fig. (a), where is the peak current, is the peak voltage, and is the voltage when the current first becomes negligible. The input signal is assumed to have a saturated ramp waveform with a rise time of . To facilitate manual analysis, we have further assumed this ramp input can be approximated by a step waveform, as shown in Fig. (b), where the sizes of the shadowed areas are matched.

Fuente: http://www.eecs.umich.edu/~mazum/PAPERS-MAZUM/tvlsi_ntd.pdf

Mejoras en los niveles de ruido

Pero el orden establecido está cambiando; las exigencias cada vez mayores de un funcionamiento de bajo ruido en el diseño de los apara­tos electrónicos de uso general está forzando la aparición de nuevas ge­neraciones de circuitos integrados para amplificadores de bajo ruido que ofrecen mejor rendimiento ge­neral. Históricamente, la creación de un amplificador de bajo ruido ha­cía necesario que los diseñadores de circuitos integrados intercambiaran otros aspectos del funcionamiento como la velocidad, la corriente de polarización de entrada y el consumo de la energía. El tamaño del dado y de la cápsula de los dispositivos de bajo ruido tienden también a ser mayores que los de los amplificadores de uso general. En las aplicaciones de bajo ruido tradicionales, como en las comunicaciones por satélite, radar o GSM inalámbrico, tales inconvenien­cias han sido secundarias a la impor­tancia de obtener el rendimiento de ruido requerido. Sin embargo, con las realidades comerciales modernas fre­cuentes en las últimas generaciones de aplicaciones de bajo ruido, surgen requisitos necesarios de bajo ruido de tensión y de bajo ruido de corriente, además de baja energía, precio eco­nómico y pequeño tamaño.

Otras exigencias importantes que afectan a los sistemas modernos in­cluyen el soporte de la oscilación de la tensión de entrada o salida de un carril a otro, para potenciar al máxi­mo el rango dinámico de la señal ya que los amplificadores deben operar a partir de unas tensiones de alimen­tación del sistema progresivamente inferiores. Otros requisitos incluyen el rechazo de la alimentación de alta potencia, por ejemplo en los produc­tos diseñados para operar a partir de una tensión de batería no regulada. Estos deben también operar sobre la gama total de tensión útil de la batería, ya que la tensión de alimen­tación decae progresivamente del nivel totalmente cargado. Satisfacer todos estos requisitos en un solo am­plificador es un reto.

Las innovaciones del proceso en las tecnologías bipolar, JFET y CMOS han posibilitado nuevas familias de dispositivos que muestran propieda­des muy optimizadas. Un ejemplo: ­­­­los amplificadores bipolares líderes están adoptando una nueva tecnología de aislamiento por zanja en lugar de la estructura tradicional de capa de difusión para obtener una densidad de transistor mayor por dado. Esta tecnología ofrece mayor velocidad, adaptación, linealidad y estabilidad, además de reducir el ruido producido por la tensión y la corriente. Los beneficios incluyen menor consumo de energía, operar sobre una gama extendida de temperaturas sin que se requieran disipadores térmicos, y que los encapsualdos sean más pequeños, con lo cual se pueden obtener densidades mayores en los diseños de canal múltiple.

Los avances en la tecnología de fabricación JFET incluyen la cons­trucción de transistores multipuer­ta para el rendimiento óptimo por área de transistor, lo cual ha permi­tido reducir el ruido de la tensión manteniendo imultáneamente un ruido de corriente ultra bajo. Con un ruido de tensión en el rango de 4-6nV/√Hz y un ruido de corriente de menos de 1fA/√Hz, los disposi­tivos de la última generación han obtenido un ruido total bajo sobre una amplia gama de impedancia de transductor. Presentan una solución especialmente robusta cuando se tratan de amplificar señales de bajo nivel procedentes de generadores de impedancia alta, especialmente de transductores capacitivos, como los hidrófonos, los acelerómetros de precisión o los fotodiodos.

El desarrollo del amplificador CMOS se está también enfocando en los avances en el nivel de silicio para eliminar los compromisos entre aspectos tales como baja derivación y bajo ruido, que también han sido difíciles de combinar en un solo dis­positivo. Otros avances de procesos incluyen el silicio con aislador (SOI) BiCMOS, que ofrece una precisión mejorada de CC, un bajo consumo de la energía y bajo ruido de tensión. Diseñados para tensiones de alimen­tación de 0,9V-12V, que incluye la optimización para una operación de 3,3V-5V, permiten la interconexión directa al convertidor A/D además de la compatibilidad con la química de la batería, como las de ión de Li, ha­ciendo que sean muy adecuados para utilizar en los dispositivos portátiles.

Fuente: http://www.redeweb.com/_txt/641/60.pdf

Diego A. Cáceres M.  C.I 19.235.570

CRF

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Noise in Circuits

Noise in Circuits

It is the purpose of this article to give the reader an introduction to understanding noise in electronic circuits, why it happens, and how to read noise specifications. The latter are not usually explained in a way that makes sense to the uninitiated, so it is hoped that this article will assist those trying to make some sense of it all.

Noise has enormous nuisance value with sensitive (i.e. high gain) circuits, but the information provided by most IC and transistor makers does not always make the choice of the most suitable device easy. Certainly, there is copious information, but explanations of what it means and how to apply it are few and far between.

This short article will hopefully clear up some of the confusion. By nature, it is rather more technical than I generally prefer, but this is unavoidable for a passably thorough understanding of the subject.

In this context, noise refers only to circuit noise, and not hum, buzz or other extraneous outside influences. These are usually the result of bad (or misguided) earthing practices, or signal wiring running close to magnetic field or harmonic generating items such as transformers and bridge rectifiers. Also to blame can be radio frequency interference, which will often cause problems if adequate (and appropriate) precautionary measures are ignored.

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Noise Figure

Noise is inherent in all electronic circuitry, and comes in three basic flavours:

• Thermal noise
• Shot noise
• Flicker (l/f) noise

Thermal noise is "white" in character (has a constant energy per unit bandwidth) and is generated by the thermal agitation of electrons in a conductor. The typical sound is hiss, hopefully at a low level so that it does not intrude on the programme material. It is calculated using Nyquist's relation:

V²R = 4k * T * R * f Where ...
V²R = mean square noise voltage k = Boltzmann constant (1.38 x 10^-23) T = Absolute temperature (Kelvin) R = Resistance in ohms f = Noise bandwidth in Hertz

Without even performing any calculations, we can see that the noise from a resistor is proportional to its resistance and temperature. Operating resistors at elevated temperatures in input stages is obviously undesirable, as are high resistance values. This also applies to any other resistive device, such as the voice coil of a dynamic (magnetic) microphone, the coils of a guitar pickup, or a vinyl disc pickup cartridge.

Shot noise is also white, and is inherent in semiconductor devices. It is primarily caused by the changes in molecular energy levels as a semiconductor device conducts.

Flicker noise is a low frequency effect, and as such is not so much of a problem with audio circuits. It becomes worse as frequency is reduced, and this can be seen in some data sheets. At the lower frequency extremes, the noise level increases.

Explanations
Before we continue, there are a couple of terms that need explanation.

Firstly, the term 'dBv' refers to decibels relative to 1V RMS, and 'dBu' means decibels relative to 775mV. This is also known as dBm, and relates to the old convention of 1mW into a 600 Ohm load. This was common in telephony (and still is in some cases), but is of little relevance to audio applications. However, we are stuck with it. 0dBv is equivalent to +2.2dBu.

Secondly, noise is commonly referred to the input of an amplifier circuit. This allows the instant calculation of output noise by simply subtracting the dB figures. So an amplifier with an 'Equivalent Input Noise' (EIN) of -120dBu having a gain of 40dB will have an output noise of -80dBu (120 - 40). This is the equivalent of 80dB Signal to Noise ratio (S/N) relative to 0dBu. Many equipment manufacturers will state S/N relative to maximum output, thereby gaining perhaps 10dB better figures. This is actually meaningless, since no-one will operate equipment at the maximum level, and the average will be considerably less.

Thirdly, it is commonly accepted that the minimum theoretical input noise (EIN) for any amplifier is -129dBu. Although not explicitly stated, this implies that the input will be terminated with a resistance. Typically, a 200 ohm source resistor will give this figure at 25°C. Sometimes, a short circuit is used instead, and this gives better apparent noise performance. A short circuit is actually meaningless though, since no real-world signal sources have zero impedance. Some do come close though, so the amplifier should always be terminated with an impedance that matches (as closely as possible) the output impedance of the signal source. This should be stated in any specification.

This means that a perfect (as noiseless as it is possible to be) amplifier with a gain of 40dB and a 600 ohm source impedance will have an output noise level of -89dBu, and if the gain were to be increased to 60dB, then output noise will be -69dBu.

It is the nature of noise that it does not add in the same way as two equal frequencies. Because of its random nature, two equal noise voltages will increase the output by only 3dB, not 6dB as might be expected. As a result, we can be reasonably sure that it is the input noise of the most sensitive section of a preamp that will set the final limit to the signal to noise ratio of the entire unit.

The way the noise figure of an opamp is commonly described is something else that needs a little explanation, since it is hardly specified in terms that most constructors will be able to relate to. The data sheet telling you that the "noise figure is 5nV/√Hz" is not very friendly. To get this into something we can understand, first we need to take the 'square root of Hz' and make some sense of it. The audio bandwidth is taken as 20Hz to 20kHz, so the square root of this is ...

√20,000 = 141 (it is not worth the effort of subtracting the 20Hz, so 141 is close enough)

With a noise figure of 5nV / √Hz, the equivalent input noise (EIN) is therefore ...

5nV x 141 = 707nV

If we assume a typical gain of a sensitive microphone stage (for example) as 100 (40dB) and an output level of 1V (0dBv), this means that the output noise equals the input noise, multiplied by gain. Signal to noise ratio can then be calculated ...

707nV x 100 = 70.7uV (EIN = -120.8dBu) Signal to noise (dB) = 20 x log (1V / 70.7uV) = 20 x log (14144) = 83dB

We can also calculate this using dB alone.

EIN = -120.8dBu Gain = 40dB S/N = 120.8 - 40 = 80.8 (ref 0dBu), or 80.8 + 2.2 = 83dB (ref 0dBv)

For low level preamps (such as microphone or moving coil phono pre-amplifiers), it is common to specify the EIN only, allowing the user to calculate the noise for any gain setting, since it changes as the gain is varied. The same amplifier as above with unity gain will have a theoretical signal to noise ratio of 123dB (relative to 1V). All of this assumes that the passive components (especially resistors) do not contribute any noise. This is false, as any device operating at a temperature above 0K (zero Kelvin, absolute zero, or about -273° Celsius) generates noise, however the contributions of passive components are relatively small with quality devices provided resistance is kept as low as possible, and voltages minimised.

Remember that a 'perfect' amplifier (contributing noise at the theoretical minimum possible), will have an equivalent input noise of -129dBu .This means that with a gain of 60dB, the best possible signal to noise ratio will be 69dB relative to 775mV (or 71.2 ref 0dBv).

As an experiment, I built a three opamp precision microphone preamp using 1458 opamps (equivalent to a dual uA741). These have a noise input figure of about 4uV - this translates to about 30 to 35nV / √Hz, or nearly 20dB worse than the NE5534A. With a gain of 46dB (200), the circuit managed a signal to noise ratio of 65dB, referred to 0dBv (1 Volt RMS). The apparently better than expected S/N ratio is because the bandwidth was so limited because of the opamps I used for this test.

I measured a S/N ratio of better than 80dB (about 82dB) again at a gain of 46dB using LM833 opamps (dual version of the NE5534). When I say that I measured this, it was with extreme difficulty. Because of the low noise, my test instruments were at their limits, so I had to guess a bit. The theoretical 'best possible' at this gain is 85.2dB referred to 0dBv, or -83dB ref. 0dBu.

Search carefully for devices with low noise for sensitive circuitry, and make sure they also have the bandwidth needed to achieve high gains. LM833 or NE5532 dual opamps are an excellent choice for low noise, but they also have wide bandwidth and can be troublesome to keep stable. Do not be tempted to use lesser devices, since their bandwidth is too limited - the 1458 was 3dB down at only 8kHz, and died rapidly after that.

In some cases, it will be found that better noise performance can be obtained using discrete opamps - built using individual components. A common technique for low noise is to select transistors based on their noise data, which will indicate the optimum collector current for a given source impedance.

Then, by using multiple devices in parallel, the noise is reduced further. Two transistors in parallel will have a noise level 3dB better than a single device. Using four will reduce this by another 3dB, and eight will give a further 3dB reduction. This is the theory behind it, but of course it will never be as good as ideal theory might indicate. It is generally considered (based on the many such designs I have seen) that between 2 and a maximum of six devices in parallel will achieve the best overall compromise. Project 25 shows a couple of designs using this method, and has some descriptive text explaining the two (very different) techniques. Project 66 gives the circuit diagram for a microphone preamplifier that uses a discrete front end to obtain low noise. No devices are paralleled as such, although the two sections appear in parallel to the following opamp.

Other Stuff
For all resistors in low noise input circuits, you absolutely, positively, must use 1% tolerance resistors, which will be metal film for lowest noise.

Many noise tests are performed using A-weighting, which introduces a filter prior to measurement. The theory of this is that it compensates for the ear's natural rolloff at low and high frequencies, and makes the measurement 'meaningful'. While the idea is quite sound in principle, I do not believe that this should be done, as not everyone is scrupulous about stating that this technique has been used, so results can be very misleading. An A-weighting filter is described in the ESP Project Pages (Project 17), along with an extensive description of the theory behind this practice.

---

Noise In Digital Equipment

For each digital bit, the relative noise floor is lowered by 6dB. A 1 bit system is of little use, and it is necessary to go to a minimum of 8 bits before even ordinary speech is intelligible - not acceptable, but intelligible. This gives a noise floor of 48dB - about what you would expect from the modern telephone system. Even there, speech is digitised at 16 bits (using an 8kHz sampling rate), and then compressed digitally to 8 bits.

(BTW, Worldwide, there are two different digital compression systems used - A-Law, used by all European countries, much of South America, Australia and New Zealand etc. u-Law (as in mu, the Greek letter) is used in the US, Canada and Japan. Prior to digital to analogue conversion, the signal is returned to the 16 bit format. This has nothing to do with noise, I just thought I'd mention it.)

Some digital answering machines use 8 bit digitisation, which explains why they sound so disgusting. Even though the noise floor is (barely) low enough, there is an insufficient number of discrete levels to faithfully reproduce speech. 8 bits only provides 256 discrete levels, and it has been generally accepted that anything less than 12 bits is unacceptable (4096 discrete levels). This is easily verified by recording something on your PC at the various available bit rates and making a comparison.

Minimum Digital Noise = 20 * Log₁₀(number of discrete levels)

When professional digital recording systems were first introduced they were 16 bit. Although this gives a theoretical noise floor 96dB below the maximum level, in reality 90dB was more likely. If maximum level corresponds to +4dBu, this indicates a noise level for each digital channel output of -86dBu.

Noise = 20 * Log₁₀65535 = -96.33dB

In the sound recording industry, the relative differences between analogue tape and digital recording must be considered. In an analogue machine, it is the tape that clips, which it does in a 'soft' manner, introducing predominantly low order harmonics. These are relatively inaudible, provided the duration is kept short (1ms or so), such as on transients.

A digital system by comparison clips suddenly and with great clarity, and it is essential to leave sufficient headroom to prevent this. If 10dB of headroom is left below maximum level to allow for transients (I would suggest this as a workable minimum), then this implies that the noise level actually present at the output of the digital playback system is -80dBu, relative to nominal (average) playback level.

Many digital systems now have 20 bit or greater resolution, although generally only 20 bits is achieved in practice. This reduces the theoretical noise floor by a further 4 bits, or 24dB. Therefore the noise level at the output of such a machine should be -110dB. Allowing the same 10dB headroom rule as above, this gives a final output noise figure of about -100dB. It is possible in many cases that the associated analogue circuitry within the digital system will be worse than this figure, so the final noise figure is somewhat unpredictable.

Materia: CRF

Nombre: Carlos L. Briceño R

Low noise, bandwidth compensated transimpedance amplifier

What is claimed is:

1. A low noise preamplifier circuit comprising:

a differential amplifier having a complimentary input and a complimentary output;

a first resistor and a second resistor, said first resistor and second resistor being coupled across said differential amplifier from input to output, providing negative feedback, said first resistor and second resistor having a substantially equal resistance value; and

a first capacitor and a second capacitor, said first capacitor and said second capacitor being coupled across said differential amplifier from input to output providing positive feedback, said first capacitor and said second capacitor having a substantially equal capacitance value, said capacitance value being selected to provide bandwidth compensation for an input capacitance applied to said complimentary input, wherein said resistance value is related to said capacitance value by the equation, CP≅2Ci/A-1/(2πB⋅Rf), where Cp is said capacitance value, Ci is the value of the input capacitance, A is a gain of said differential amplifier circuit, B is a selected operating bandwidth and Rf is said resistance value.

2. A low noise preamplifier circuit compensated for an applied input capacitance, the preamplifier comprising:

an amplifier circuit;

a first resistor and a second resistor for providing negative, resistive feedback across said amplifier circuit, said first resistor and second resistor having a substantially equal resistance value; and

a first capacitor and a second capacitor for providing positive, capacitive feedback across said amplifier circuit, said first capacitor and said second capacitor having a substantially equal capacitance value, wherein said resistance value is related to said capacitance value, said relationship being substantially defined by the equation CP≅2Ci/A-1/(2πB⋅Rf), where Cp is said capacitance value, Ci is the value of the input capacitance, A is a gain of said differential amplifier circuit, B is a selected operating bandwidth and RF is said resistance value.


3. A low noise, bandwidth compensated optical front end circuit comprising:

a differential amplifier circuit, said differential amplifier circuit having a first input terminal, a second input terminal, a first output terminal and a second output terminal;

a photodetector having an associated capacitance value, said optical detector being operatively coupled to said first input terminal and said second input terminal of said differential amplifier circuit;

a first resistor, said first resistor connected between said first input terminal and said first output terminal;

a second resistor, said second resistor connected between said second input terminal and said second output terminal;

a first capacitor, said first capacitor being connected between said first output terminal and said second output terminal; and

a second capacitor, said second capacitor being connected between said second input terminal and said first output terminal, said first capacitor and said second capacitor having a substantially equal capacitance value, said value selected to compensate the effect of the capacitance value associated with said photodetector, wherein the value of said first resistor and said second resistor is related to the value of said first capacitor and said second capacitor, said relationship being substantially defined by the equation CP≅2Ci/A-1(2πB⋅Rf), where Cp is the value of said first and second capacitor, Ci is the value of the capacitance of said photodetector, A is a gain of said differential amplifier circuit, B is a selected operating bandwidth and Rf is the value of said first and second resistors.

4. A method of compensating an amplifier circuit in the presence of an applied input capacitance comprising the steps:

determining a gain of the amplifier, a transimpedance resistance value in feedback with the amplifier and a value of the input capacitance;

selecting a desired operating bandwidth of the amplifier; and

calculating a value of at least one compensation capacitor applied in a positive feed back arrangement across the amplifier by applying a formula, CP≅2Ci/A-1(2πB⋅Rf), where Cp is the value of said compensation capacitor, Ci is the value of the input capacitance, A is a gain of the amplifier circuit, B is the selected bandwidth and Rf is the value of the transimpedance resistance.

Nombre: Carlos L. Briceño R
Materia: CRF
Fuente: http://www.patentstorm.us/patents/5982232/description.html

High-sensitivity, low-noise transistor amplifier

A high-gain, low-noise transistor amplifier comprises an input, an output, and first and second field effect transistors each having a gate, a drain, and a source and being formed in a common semiconductor substrate. The second transistor is a depletion mode transistor if it is of the same conductivity type as the first but is an enhancement mode transistor if it is of opposite conductivity type with respect to the first. In an amplifier configuration, the input is coupled to the gate of the first transistor, the source of the first transistor is coupled to the gate of the second transistor, the source of the second transistor is coupled to the output, and there is a direct-coupled feedback path from the source of the second transistor to the drain of the first transistor. At least the first transistor is formed in an isolated well of conductivity opposite to that of the substrate in the semiconductor substrate and its source is coupled directly to that well.

1. An amplifier comprising:
an input, an output, and first and second field effect transistors each having a gate, a drain, and a source and being formed on a common semiconductor substrate;
the second transistor being of a mode selected from a group consisting of depletion mode and enhancement mode;
the first and second transistors being of conductivity types selected from a group consisting of the same conductivity types and opposite conductivity types;
the second transistor being depletion mode with first and second transistors being of the same conductivity types;
the second transistor being enhancement mode with first and second transistors being of opposite conductivity types;
means coupling the input to the gate of the first transistor;
means coupling the source of the first transistor to the gate of the second transistor;
means coupling the source of the second transistor to the output; and
a direct-coupled feedback path from the source of the second transistor to the drain of the first transistor.


2. The amplifier of claim 1 in which the first transistor is formed in an isolated well in the substrate, the well being of opposite conductivity type with respect to the substrate, and which further comprises means coupling the source of the first transistor to its own well.

3. The amplifier of claim 1 further comprising means for coupling a voltage source between the sources and drains of both of the transistors.

4. The amplifier of claim 3 further comprising means for coupling a first substantially constant current source to the source of the first transistor and means for coupling a second substantially constant current source to the source of the second transistor.

5. The amplifier of claim 4 in which the first transistor is formed in an isolated well in the substrate, the well being of opposite conductivity type with respect to the substrate, and which further comprises means coupling the source of the first transistor to its own well.

6. An amplifier comprising:
an input, an output, and first and second field effect transistors of the same conductivity type each having a gate, a drain, and a source and being formed on a common semiconductor substrate, the second transistor being a depletion mode transistor;
means coupling the input to the gate of the first transistor;
means coupling the source of the first transistor to the gate of the second transistor;
means coupling the source of the second transistor to the output; and
a direct-coupled feedback path from the source of the second transistor to the drain of the first transistor.


7. The amplifier of claim 6 in which both of the transistors are formed in isolated wells in the substrate, the wells being of opposite conductivity type from the substrate, and which further comprises means coupling the source of each of the transistors to its own well.

8. The amplifier of claim 6 further comprising means for coupling a voltage source between the sources and drains of both of the transistors.

9. The amplifier of claim 8 further comprising means for coupling a first substantially constant current source to the source of the first transistor and means for coupling a second substantially constant current source to the source of the second transistor.

10. The amplifier of claim 9 in which both of the transistors are formed in isolated wells in the substrate, the wells being of opposite conductivity type from the substrate, and which further comprises means coupling the source of each of the transistors to its own well.

11. An amplifier comprising:
an input, an output, and first and second field effect transistors of opposite conductivity types each having a gate, a drain, and a source and being formed on a common semiconductor substrate, the second transistor being an enhancement mode transistor;
means coupling the input to the gate of the first transistor;
means coupling the source of the first transistor to the gate of the second transistor;
means coupling the source of the second transistor to the output; and
a direct-coupled feedback path from the source of the second transistor to the drain of the first transistor.


12. The amplifier of claim 11 in which the first transistor is formed in an isolated well in the substrate, the well being of opposite conductivity type from the substrate, and which further comprises means coupling the source of the first transistor to its own well.

13. The amplifier of claim 11 further comprising means for coupling a voltage source between the sources and drains of both of the transistors.

14. The amplifier of claim 13 further comprising means for coupling a first substantially constant current source to the source of the first transistor and means for coupling a second substantially constant current source to the source of the second transistor.

15. The amplifier of claim 14 in which the first transistor is formed in an isolated well in the substrate, the well being of opposite conductivity type from the substrate, and which further comprises means coupling the source of the first transistor to its own well.

16. An amplifier comprising:
a semiconductor substrate;
first and second separated field effect transistors of the same conductivity type each of which is formed in the substrate and having a drain, a source, and a gate, the second transistor being a depletion mode transistor;
first and second constant current sources formed in the substrate;
the source of the first transistor being coupled to the first constant current source and the gate of the second transistor;
the gate of the first transistor being adapted to serve as an input of the amplifier;
the source of the second transistor being coupled to the second constant current source and to an output of the amplifier; and
a direct-coupled feedback path between the source of the second transistor and the drain of the first transistor.


17. An amplifier comprising:
a semiconductor substrate;
first and second separated field effect transistors of opposite conductivity types each of which is formed in the substrate and having a drain, a source, and a gate, the second transistor being an enhancement mode transistor;
first and second constant current sources formed in the substrate;
the source of the first transistor being coupled to the first constant current source and the gate of the second transistor;
the gate of the first transistor being adapted to serve as an input of the amplifier;
the source of the second transistor being coupled to the second constant current source and to an output of the amplifier; and
a direct-coupled feedback path between the source of the second transistor and the drain of the first transistor.

Description:

FIELD OF THE INVENTION

This invention relates generally to high-sensitivity, low-noise transistor amplifiers and, more particularly, to transistor amplifiers of the type used for CCD (Charge Coupled Device) charge detection.

BACKGROUND OF THE INVENTION

A well known and widely used configuration for CCD charge detection is called a Floating-Diffusion Amplifier (FDA). In this configuration, the signal charge from the CCD is dumped into a reverse biased, floating diffusion node that is periodically reset to a fixed potential. The presence of this signal charge changes the voltage across the diffusion node by a relation inversely proportional to the effective capacitance of the floating diffusion node (i.e., the input capacitance of the amplifier). The noise introduced by a non-ideal reset process is related to the square root of that same capacitance. The signal-to-noise performance of the detector is thus improved if the input capacitance of the amplifier can be reduced. In the past, device processing factors have limited the amount by which such input capacitance can be reduced. For this reason, such factors have also limited the amount by which signal to noise performance can be improved.

SUMMARY OF THE INVENTION

The invention is directed to a transistor amplifier whose reduced input capacitance makes it particularly suitable for use in low-noise CCD charge-detection.

In its broader aspects, the invention is directed to a high-gain, low-noise, two stage amplifier comprising an input, an output, and first and second source follower field effect transistors each having a gate, a drain, and a source. Both transistors are formed in a common semiconductor substrate. The second transistor is a depletion mode (i.e., buried channel) transistor if it is of the same conductivity type as the first but is an enhancement mode (i.e., surface channel) transistor if it is of opposite conductivity type from the first. In an amplifier configuration according to the invention, the input is coupled to the gate of the first transistor, the source of the first transistor is coupled to the gate of the second transistor, the source of the second transistor is coupled to the output, and there is a direct-coupled feedback path from the source of the second transistor to the drain of the first transistor. Such a configuration provides a significant reduction in the input capacitance of the two stage amplifier and, hence, a significant improvement in signal-to-noise performance.

One important embodiment of the invention is a high-gain, low-noise, two stage amplifier comprising an input, an output, and first and second depletion mode source follower field effect transistors of the same conductivity type each having a gate, a drain, and a source and being formed on a common semiconductor substrate. In this embodiment of the invention, the second transistor is a depletion mode transistor, the input is coupled to the gate of the first transistor, the source of the first transistor is coupled to the gate of the second transistor, the source of the second transistor is coupled to the output, and there is a direct-coupled feedback path from the source of the second transistor to the drain of the first transistor. In order to reduce input capacitance still further, both transistors are formed in isolated wells in the substrate of opposite conductivity type from the substrate and have the source of each transistor coupled directly to its own well.

Another important embodiment of the invention is a high-gain, low-noise, two stage amplifier comprising an input, an output, and first and second enhancement mode source follower field effect transistors of opposite conductivity types each having a gate, a drain, and a source and being formed in a common semiconductor substrate. In this embodiment of the invention, the second transistor is an enhancement mode transistor, the input is coupled to the gate of the first transistor, the source of the first transistor is coupled to the gate of the second transistor, the source of the second transistor is coupled to the output, and there is a direct-coupled feedback path from the source of the second transistor to the drain of the first transistor. In order to reduce input capacitance still further, the first transistor is formed in an isolated well in the substrate of opposite conductivity type from the substrate and has its source coupled directly to its own well.

The invention will be better understood from the following detailed description of the prior art and two specific embodiments, taken in the light of the accompanying drawing and the appended claims.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a schematic diagram of a floating-diffusion amplifier of a type commonly found in the prior art;

FIG. 2 is a schematic diagram of one two stage transistor amplifier embodying the invention;

FIG. 3 is a schematic diagram of another two stage transistor amplifier embodying the invention;

FIG. 4 is a general illustration of a type of semiconductor structure used in connection with the embodiment of the invention shown in FIG. 2; and

FIG. 5 is a general illustration of a type of semiconductor structure used in connection with the embodiment of the invention shown in FIG. 3.

DETAILED DESCRIPTION

FIG. 1 shows a floating-diffusion amplifier 10 whose principal components are a first depletion mode n-channel field effect transistor 12 and a second depletion mode n-channel field effect transistor 14. Depletion mode transistors are also known as buried channel transistors and are normally in the conducting or on state. Each of transistors 12 and 14 includes connections, as illustrated, to a gate G, a drain D, a source S, and the transistor body (the substrate or the well, as applicable) B. The direction of the arrow associated with each body B indicates, in accordance with convention, that both transistors 12 and 14 are n-channel devices. For p-channel devices, the arrow would point in the opposite direction. As shown, the body of each of transistors 12 and 14 is connected to a common ground.

In amplifier 10, transistor 12 is connected as a source follower input stage and transistor 14 is connected as a source follower output stage. Specifically, an input terminal IN of amplifier 10 is connected to the gate of transistor 12, the source of transistor 12 is connected to the gate of transistor 14, and the source of transistor 14 is connected to an output terminal OUT of amplifier 10. The drains of both transistors 12 and 14 are connected to a positive voltage source V _DD , while the sources of both transistors 12 and 14 are connected through respective constant current (i.e., high impedance) sources to a voltage source V _SS which is negative with respect to source V _DD .

As illustrated, the first constant current source in amplifier 10 may, by way of example, comprise a depletion mode n-channel field effect transistor 16 having respective gate, drain, source, and body connections and the second constant current source may, by way of example, comprise a depletion mode n-channel field effect transistor 18 having respective gate, drain, source, and body connections. The drain of transistor 16 is connected to the source of transistor 12, while both the gate and the source of transistor 16 are connected to voltage source V _SS . Similarly, the drain of transistor 18 is connected to the source of transistor 14, while both the gate and the source of transistor 18 are connected to voltage source V _SS . As illustrated, the body of each of transistors 16 and 18 is connected to the same common ground as those of transistors 12 and 14.

A CCD charge packet is supplied to amplifier 10 through input terminal IN and controlled by another depletion mode n-channel field effect transistor 20 and a diode 22. Like the other transistors in amplifier 10, transistor 20 has gate, source, drain, and body connections. As shown, the source of transistor 20 is coupled to input terminal IN and the drain of transistor 20 is coupled to a positive voltage source V _RD . A control signal OR is supplied to the gate of transistor 20 to reset input terminal IN to V _RD . The cathode of diode 22 is connected to the gate of transistor 12, while the anode is connected to ground. Because transistor 20 is normally conducting, diode 22 is normally reverse biased by voltage source V _RD . Control signal OR consists of a train of pulses each of which selectively biases transistor 20 off. This allows input terminal IN to assume a potential determined by the charge placed thereon by a CCD (not shown).

The presence of a CCD charge at the gate of transistor 12 changes the voltage across the input of the source follower formed by transistor 12 by the equation Vs=qNs/Cfd,

where Ns is the number of charge carriers, Cfd is the effective capacitance of the floating diffusion node, and q is the charge of an electron. The noise introduced by a non-ideal reset process is given by the equation =(kTCfd) ¹ /2 /q.

Therefore, by reducing the capacitance Cfd, the signal-to-noise performance (Ns/) of the detector may be improved. It should be noted that, although this so-called kTC noise may be removed by a technique known as correlated double sampling, the actual signal-to-noise ratio includes several other components as well. The same conclusion holds, however, that the signal-to-noise ratio is improved by reducing Cfd. In order to make amplifier 10 more suitable for use for low-noise CCD charge detection there is, therefore, a need to reduce the input capacitance of amplifier 10 more than previously known techniques readily permit.

The input capacitance of the first source follower stage (transistor 12) of amplifier 10 is given by the equation Cin ₁₀ =(1-Av1)Cgs ₁₂ +Cgd ₁₂ +Cgb ₁₂ ,

where Av1 is the small-signal voltage gain of the first stage (transistor 12) and Cgs ₁₂ , Cgd ₁₂ , and Cgb ₁₂ are the respective gate-to-source, gate-to-drain, and gate-to-body capacitances of transistor 12. From this expression, it can be seen that to reduce Cin ₁₀ , it is desirable to have Av1 close to unity and to have small values of Cgs ₁₂ , Cgd ₁₂ , and Cgb ₁₂ . Cgs ₁₂ , Cgd ₁₂ , and Cgb ₁₂ can be minimized (for a particular process) by reducing the physical size of transistor 12. Av1, however, is limited by processing to values of from about 0.8 to 0.9 by the so-called body effect of the transistor. The expression for the gain Av1 can be shown to be given by the equation Av1=[1+(gds12+gds16+gmb12)/gm12] ^-1 ,

where gds12 and gds16 are the drain-to-source output conductances of transistors 12 and 14 and gm12 and gmb12 are the respective top-gate and back-gate transconductances of transistor 12, respectively. The ratio of gmb12 to gm12 is known as the body effect parameter X.

FIG. 2 illustrates an amplifier 30 which embodies various aspects of the invention. Amplifier 30 is like amplifier 10 in that its principal components are a first depletion mode n-channel field effect transistor 32 and a second depletion mode n-channel field effect transistor 34. Transistors 32 and 34 are both formed, typically, in a common semiconductor substrate, which is shown in FIG. 4. Each of transistors 32 and 34 includes connections, as illustrated, to a gate G, a drain D, a source S, and the transistor body (the respective well, in this instance) B. The direction of the arrow associated with each body B indicates, in accordance with convention, that both transistors 32 and 34 are n-channel devices. One aspect of difference between amplifiers 10 and 30, however, is that in amplifier 30 both transistors 32 and 34 are formed in isolated p-wells in the common semiconductor substrate and the source node of each is tied to the respective p-well.

In amplifier 30, transistor 32 is connected as a source follower input stage and transistor 34 is connected as a source follower output stage. Specifically, an input terminal IN of amplifier 30 is connected to the gate of transistor 32, the source of transistor 32 is connected to the gate of transistor 34, and the source of transistor 34 is connected to an output terminal OUT of amplifier 30. The drain of transistor 34 is connected to a positive voltage source V _DD , while the sources of both transistors 32 and 34 are connected through respective constant current (i.e., high impedance) sources to a voltage source V _SS which is negative with respect to source V _DD .

As illustrated, the first constant current source in amplifier 30 may, by way of example, comprise a depletion mode n-channel field effect transistor 36 having respective gate, drain, source, and body connections. The second constant current source may, also by way of example, comprise a depletion mode n-channel field effect transistor 38 having respective gate, drain, source, and body connections. The drain of transistor 36 is connected to the source of transistor 32, while both the gate and the source of transistor 36 are connected to voltage source V _SS . Similarly, the drain of transistor 38 is connected to the source of transistor 34, while both the gate and the source of transistor 38 are connected to voltage source V _SS . Both transistors 36 and 38 may be formed on the same semiconductor substrate (not shown) as transistors 32 and 34. Both transistors 36 and 38 are formed in isolated p-wells and the source node of each is tied to the respective p-well. In accordance with one important aspect of the invention, a direct-coupled feedback path 44 is provided between the source of transistor 34 and the drain of transistor 32.

A CCD charge packet is supplied to amplifier 30 through input terminal IN and controlled by another depletion mode n-channel field effect transistor 40 and a diode 42. Like the other transistors in amplifier 30, transistor 40 has gate, source, drain, and body connections. As shown, the source of transistor 40 is coupled to input terminal IN and the drain of transistor 40 is coupled to a positive voltage source V _RD . A control signal OR is supplied to the gate of transistor 40 to reset input terminal IN to V _RD . The cathode of diode 42 is connected to the gate of transistor 32, while the anode is connected to ground. Because transistor 40 is normally conducting, diode 42 is normally reverse biased by voltage source V _RD . Control signal OR consists of a train of pulses each of which shuts transistor 20 off. This allows input terminal IN to assume a potential determined by the charge placed thereon by a CCD (not shown).

In amplifier 30, the body effect parameter X is eliminated from the gain expression as a result of transistors 32 and 34 having been formed in isolated p-wells and by tying their source nodes to those p-wells. This eliminates the small-signal voltage variation from body to source, vbs, and improves the amplifier's linearity (since X is inversely proportional to the square root of the source to body voltage vbs). Also, gdsl is effectively reduced by the small-signal voltage gain of the second stage source follower (transistor 34), Av2. The gain of the first stage (transistor 32) of this new configuration can be shown to be given by the equation Av1={1+[gds36+(1-Av2)gds32]/gm1} ^-1

and the gain of the second stage (transistor 34) by the equation Av2=[1+(gds34+gds38/gm34] ^-1 .

Therefore, feeding back the output of the second stage (transistor 34) to the drain of the first stage (transistor 32) through feedback path 44 further improves the gain of the first stage (transistor 32). Even more importantly, though, the feedback effectively reduces the gate-to-drain capacitance of the first stage (transistor 32). Additionally, since the body of transistor 32 is tied to its source, (i.e., vbs=0), vgb is equal to vgs. Hence, the gate-to-body capacitance Cgb ₃₂ is reduced in the same manner as Cgs ₃₂ . In can be shown that the input capacitance for this configuration is given by the equation Cin ₃₀ =(1-Av1)Cgs ₃₂ +(1-Av1Av2)Cgd ₃₂ +(1-Av1)Cgd ₃₂ .

Typical values for Av1 and Av2 of this new configuration can be as high as 0.97 to 0.99. Therefore, the amplifier 30 configuration has a lower input capacitance and, hence, a better signal to noise ratio than does such prior art as amplifier 10.

To ensure linearity, transistor 32 is kept in its saturation region of operation as defined by Vgd

FIG. 3 illustrates an amplifier 50 which embodies various aspects of the invention and is an alternative to amplifier 30. In amplifier 50, the first stage is an enhancement mode (i.e., surface channel) field effect transistor 52 and the second stage is an opposite conductivity type enhancement mode (i.e., surface channel) field effect transistor 54. More specifically, the first stage is an enhancement mode n-channel field effect transistor 52, while the second stage is an enhancement mode p-channel field effect transistor 54. Each of transistors 52 and 54 includes connections, as illustrated, to a gate G, a drain D, a source S, and the transistor body (the substrate for transistor 52 or the well for transistor 54) B. Transistors 52 and 54 are, typically, formed in a common semiconductor substrate which is shown in FIG. 5. The direction of the arrow associated with each body B indicates, in accordance with convention, that transistor 52 is an n-channel device and transistor 54 is a p-channel device. Transistor 52 is formed in an isolated p-well in the substrate. Transistor 54, which is a p-channel device, is formed directly in the common substrate as shown in FIG. 5. The source node of transistor 52 is tied, as schematically illustrated, to that transistor's isolated p-well.

In amplifier 50, transistor 52 is connected as a source follower input stage and transistor 54 is connected as a source follower output stage. Specifically, an input terminal IN of amplifier 50 is connected to the gate of transistor 52, the source of transistor 52 is connected to the gate of transistor 54, and the source of transistor 54 is connected to an output terminal OUT of amplifier 50. The source of transistor 54 is connected through a second constant current (i.e., high impedance) source to a positive voltage source V _DD , while the drain of transistor 54 is connected to a voltage source V _SS which is either less positive or negative with respect to source V _DD . The source of transistor 52 is connected through a first constant current source to voltage source V _SS . The body of transistor 54 is connected to the voltage V _SUB of the common substrate of the entire amplifier.

As illustrated, the first constant current source in amplifier 50 may, by way of example, comprise a depletion mode n-channel field effect transistor 56 having respective gate, drain, source, and body connections. The second constant current source may, also by way of example, comprise a depletion mode p-channel field effect transistor 58 having respective gate, drain, source, and body connections. The drain of transistor 56 is connected to the source of transistor 52, while both the gate and the source of transistor 56 are connected to voltage source V _SS .

The drain of transistor 58 is connected to the source of transistor 54, while both the source and the gate of transistor 58 are connected to voltage source V _DD . The body of transistor 58 is connected to the voltage V _SUB of the common substrate of the entire amplifier. In accordance with an important aspect of the invention, a direct-coupled feedback path 64 is provided from the source of transistor 54 to the drain of transistor 52.

A CCD charge packet is supplied to amplifier 50 through input terminal IN and controlled by another depletion mode n-channel field effect transistor 60 and a diode 62. Like the other transistors in amplifier 50, transistor 60 has gate, source, drain, and body connections. As shown, the source of transistor 60 is coupled to input terminal IN and the drain of transistor 60 is coupled to a positive voltage source V _RD . A control signal OR is supplied to the gate of transistor 60 to reset input terminal IN to V _RD . The cathode of diode 62 is connected to the gate of transistor 52, while the anode is connected to ground. Because transistor 60 is normally conducting, diode 62 is normally reverse biased by voltage source V _RD . Control signal OR consists of a train of pulses each of which biases transistor 60 off. This allows input terminal IN to assume a potential determined by the charge placed thereon by a CCD (not shown).

Amplifier 50 in FIG. 3 reduces effective input capacitance and affords an improved signal to noise ratio in very much the same manner as amplifier 30 in FIG. 2. In a p-well process, however, it is not possible to tie the body of transistor 54 to its source. As a result, amplifier 50 has a somewhat lower second stage gain and a somewhat higher Cin than amplifier 30.

FIG. 4 shows a portion of a semiconductor structure 70 in which amplifier 30 of FIG. 2 may be fabricated. Structure 70 comprises an n-type conductivity semiconductor substrate 72 in which two n-channel depletion mode (i.e., buried channel) transistors are shown. Included in substrate 72 are two p-wells 74 and 76. For each transistor, the respective p-well is the body. The transistor formed in p-well 74 (comparable to transistor 32 of amplifier 30 in FIG. 2) comprises a drain region 78 of n-type conductivity, a source region 80 of n-type conductivity, a buried channel region 82 of n-type conductivity connecting drain 78 and source 80, a dielectric layer 84 (typically SiO ₂ ) extending between drain 78 and source 80 on a surface of substrate 72, and a gate electrode 86 extending between drain 78 and source 80 on a surface of dielectric layer 84. The transistor formed in p-well 76 (comparable to transistor 34 of amplifier 30 in FIG. 2) includes a drain region 88 of n-type conductivity, a source region 90 of n-type conductivity, a buried channel region 92 of n-type conductivity connecting drain 88 and source 90, a dielectric layer 94 extending between drain 88 and source 90 on a surface of substrate 72, and a gate electrode 96 extending between drain 88 and source 90 on a surface of dielectric layer 94.

FIG. 5 shows a portion of a semiconductor structure 100 in which amplifier 50 of FIG. 3 may be fabricated. Structure 100 comprises an n-type conductivity semiconductor substrate 102 which includes one n-channel enhancement mode (i.e., surface channel) transistor and one p-channel enhancement mode (i.e., buried channel) transistor. Included in substrate 72 is a p-well 104, which constitutes the body of the transistor. The transistor formed in p-well 104 (comparable to transistor 52 of amplifier 50 in FIG. 3) includes a drain region 106 of n-type conductivity, a source region 108 of n-type conductivity, a dielectric layer 110 (typically SiO ₂ ) extending between drain 106 and source 108 on a surface of substrate 102, and a gate electrode 112 extending between drain 106 and source 108 on a surface of dielectric 110. The remaining transistor (comparable to transistor 54 of amplifier 50 in FIG. 3) is formed directly in substrate 102 and includes a drain region 114 of p-type conductivity, a source region 116 of p-type conductivity, a dielectric layer 120 extending between drain 114 and source 116 on a surface of substrate 102, and a gate electrode 122 extending between drain 114 and source 116 on a surface of dielectric layer 120. For this latter transistor, substrate 102 itself constitutes the body.

It is to be understood that the embodiments of the invention which have been described are illustrative. Transistors of conductivity type opposite to those shown may be employed, for example, if all diode and voltage polarities are reversed from those shown as well. In addition, transistor 32 in FIG. 2 may be an enhancement mode transistor if desired and transistor 52 in FIG. 3 may be a depletion mode transistor if desired. Numerous other arrangements and modifications may also be readily devised by those skilled in the art without departing from the spirit and scope of the invention.

Nombre: Carlos L. Briceño R

Materia: CRF

Fuente: http://www.freepatentsonline.com/5192920.html