Intrinsic noise in aggressively scaled field-effect transistors

Abstract. According to roadmap projections, nanoscale field-effect transistors (FETs) with channel lengths below 30 nm and several gates (for improving their gate control over the source–drain conductance) will come to the market in the next few years. However, few studies deal with the noise performance of these aggressively scaled FETs. In this work, a study of the effect of the intrinsic (thermal and shot) noise of such FETs on the performance of an analog amplifier and a digital inverter is carried out by means of numerical simulations with a powerful Monte Carlo (quantum) simulator. The numerical data indicate important drawbacks in the noise performance of aggressively scaled FETs that could invalidate roadmap projections as regards analog and digital applications.

Keywords: current fluctuations, classical Monte Carlo simulations, mesoscopic systems (theory)

Contents

1. Introduction

2. Intrinsic noise in quasi-ballistic devices

2.1. Analytical results for noise in analog applications

2.2. Analytical results for noise in digital (logic and memory) applications

3. Numerical results for nanoscale field-effect transistors

3.1. Device description

3.2. Numerical Monte Carlo simulation algorithm

3.3. DC results

3.4. Analog noise results

3.5. Digital noise results

4. Conclusions

Acknowledgment

References

1. Introduction

The ITRS predicts for the near future the introduction of nanoscale field-effect transistors (FET) with channel lengths below 30 nm, including novel structures with two, three or even four gates provided in order to improve the gate control over the source–drain conductance [1]. The advantages of these nanoscale FETs in overcoming the physical limits of traditional FETs are clearly established in terms of size, speed and power consumption. However, few studies deal with the noise performance of these aggressively scaled FETs. This is the main goal of this work.

At very small (a few nanometers) dimensions of FETs, two important physical features appear in the description of electron transport. On one hand, ballistic transport comes into play. For advanced FETs with channel length smaller than 30 nm, an electron crossing the channel suffers very few inelastic collisions and its total (kinetic plus electrostatic) energy is nearly constant. On the other hand, when the lateral dimensions of the channel are comparable to the de Broglie wavelength of the electron, its wave nature is manifested. The only available energies for electrons are those that provide a solution of the Schrödinger equation whose modulus is zero at the lateral boundaries. The role of such particularities in the noise performance of FET structures will be studied in this work using a powerful Monte Carlo (quantum) simulator. Although there are other sources that provide time-dependent fluctuations of the electronic current in FETs [2], when all those `spurious' sources of noise are eliminated, thermal and shot noise still remain. Therefore, we will consider only these two sources of noise within a particular 3D (bulk) FET and a 1D (quantum wire) FET.

In section 2, we provide analytical estimations for the signal-to-noise ratio (S/N) of a simple analog amplifier, and the bit–error ratio (BER) of a simple CMOS inverter. Then, in section 3, we will compute numerical results for the analog and digital applications by means of an electron device Monte Carlo simulator coupled to a full Poisson solver [3] with a novel injection model suitable for electron devices with or without quantum confinement conditions [4]. We conclude in section 4 summarizing the most important results of this work.

2. Intrinsic noise in quasi-ballistic devices

Here, we obtain analytic estimates for the noise performances in both analog and digital FET applications. Such analytic expressions for the S/N ratio and the BER will help in the understanding of the Monte Carlo numerical noise results.

2.1. Analytical results for noise in analog applications

In the present subsection we deduce an analytical expression for the S/N ratio for the analog amplifier depicted in figure 1(a).

Figure 1. (a) Schematic representation of an analog amplifier. D and S denote the drain and source respectively. (b) Equivalent FET circuit, where δI_DS(t) and I_DS(t) denote noise and signal sources respectively and G represents the FET conductance.

The current fluctuations can be extracted from the equivalent circuit shown in figure 1(b):

where G is the FET conductance, ΔV_DS is the source–drain voltage fluctuation and δI_DS denotes the intrinsic current noise. At the same time, since the FET is operated in the saturation region,

we assume that the fluctuation of the drain–source current in (1) will depend not on the drain–source voltage variation, but only on δI_DS(t). This is a reasonable approximation for the saturation region and the low-frequency limit assumed here. Thus, we can rewrite (1) as

On the other hand, using the superposition principle, V_DS and I_L can be broken down into signal (capital letters) and noise (δ). Removing signal sources from figure 1, it is easy to demonstrate that the noise current on the resistor R_L is

Equation (4) can be expressed in the frequency domain as

where H(ω) is a transfer function. Now, integrating over a bandwidth B associated with a specific amplifier configuration, the resulting total noise power is

which yields, using H(ω) = R/(R + R_L), the following result:

Note that in equations (6) and (7), we have used the corresponding power spectral density of the thermal noise (S_I), expressed in terms of the Fano factor (F):

Now, let us calculate the signal power. First, we express V_DS as

Then, we solve (9), obtaining expression for I_{R_L}:

Finally, the signal power S_{R_L} = I_{R_L}²R_L can be written as

Assuming $R \gg R_{L}$ , expressions (7) and (11) reduce respectively to

and

Finally, the signal-to-noise ratio is

The expression (14) tells us that when the current I_DS decreases or the Fano factor (F) increases, the signal-to-noise ratio is degraded.

Hereafter, we show that, in fact, the downscaling trend of CMOS technology towards low-dimensional active regions provides lower current and also higher Fano factor. For ballistic devices, only the electrons crossing the FET channel contribute to the average and the noise currents [4]. As an example, let us assume a potential barrier within a FET channel. Only those electrons energetically above this barrier will contribute to the current and noise (if tunneling can be neglected). These `hot' electrons come from the Fermi distribution tail. Thus, they are mainly uncorrelated electrons, so they provide little current but a high Fano factor (close to the uncorrelated Poisson value of F = 1), resulting in a degraded S/N ratio. Similarly, within a ballistic confined FET system, only those electrons above the confinement energy will enter the channel. In this sense, confinement introduces an additional potential barrier that makes the system deal with a `hotter' region of the fermi distribution, where noise is greater and current lower, giving rise to a degradation of the S/N ratio. On the other hand, bulk FETs do not present potential barriers linked to confinement, resulting in a better S/N ratio. In conclusion, low-dimensional FETs implicitly exhibit higher S/N ratios. Later, in section 3, numerical results obtained with a powerful Monte Carlo (quantum) simulator will be computed for the same system without some of the analytical (low-frequency) simplifications used above.

2.2. Analytical results for noise in digital (logic and memory) applications

Next we deduce analytical expressions for the BER of the digital inverter depicted in figure 2(a), taken as a simple digital circuit for analyzing the role of scaling. When a logical `1' is applied at the first inverter, the P-type transistor P1 is turned off, while the N-type transistor N1 is turned on. N1 is now working in the equilibrium region, giving a logical `0' at the input of the second inverter. Thus, N2 will be turned off while P2 will be turned on. Under these operation conditions, N1 and P2 can be equivalently defined as depicted in the figure 2(b). Transistor N1 can be modeled as the parallel combination of a signal source I_DS, a noise source δI_DS and a conductance G. On the other hand P2 can be modeled as a capacitor.

Figure 2. (a) Schematic representation of a digital inverter. (b) Equivalent circuit for N1 and P2, where δI_DS(t) and ΔI_DS(t) denote noise and signal sources respectively assuming a linear region of operation. G represents the FET conductance and C the associated capacitance for P2 transistors.

Since N1 has its channel completely open, it works within the equilibrium region of operation. Then the current fluctuations around zero mean value, I_DS(t) approx

0, are given by

where the conductance G is linked with the linear region of operation, i.e. G is roughly constant under small voltage fluctuations. Therefore, G only depends on the applied gate voltage and it can be defined on the equilibrium region, i.e. $G={\partial I_{\mathrm {DS}} / \partial V_{\mathrm {DS}} } |_{V_{\mathrm {DS}}=0}$ . The first term on the right in equation (15) corresponds to the current fluctuations associated with the voltage fluctuations in the capacitor. The second term corresponds to the intrinsic transistor noise.

Under the equilibrium conditions that we are assuming, noise in the transistor N1 is characterized by the Nyquist–Johnson thermal noise [5]. Then, the corresponding power spectral density for δI_DS(t) at low frequencies exhibits the form

We can relate variations of the current for the N1 transistor to voltage variations at the capacitor representing P2. Then, making equation (15) equal to the one corresponding to the capacitor current, the intrinsic current noise can be expressed as

The previous expression can be rewritten in the frequency domain as

Therefore, the bias fluctuations are

Combining equations (16) and (19), the total power for the bias fluctuations can be calculated by integrating the spectral density over the frequency:

A bit error appears when (during a period T_C = 1/f_c with f_c the clock frequency) the mean value of the bias fluctuations exceeds the threshold value for a logical `0'. Therefore, when we use the superior limit of the integral of expression (20) as W_t = 2πf_c, we obtain

Therefore, the bit error probability can be expressed as [6]

where A is the bias value associated with the logical value `1', and Q is the error function defined as

From (22) and (23), the BER is higher with higher clock frequencies (see the dependence of expression (22) on the clock frequency through the inverse tangent). For clock frequencies far below the intrinsic frequency (R_TC)^–1, the following simplification can be made: tan ^–1(x) approx

x. Then, the total power, obtained from expression (21), can be approximated as

It can be seen from expression (24) that under this frequency limit, there is no capacitance dependence of the BER. On the other hand, for clock frequencies higher than the intrinsic frequency (R_TC)^–1, then tan ^–1(x) approx

π/2, and the total power can be approximated as

In expression (25), the variance of the normal distribution shrinks with the capacitance value. In other words, smaller FETs will show higher error probabilities. A similar result, obtained through a different reasoning, has been presented in [7].

So far, analytical estimations for noise performance for analog and digital applications have been deduced. In fact, expressions (14) and (22) will only capture the main trends as regards the understanding of intrinsic noise behavior in nanoscale devices. In view of this, the main goal of the next section is to obtain numerical values for S/N and BER through a much more complex and detailed description of the electron dynamics. Next, we use a Monte Carlo (quantum) simulator which is a powerful and robust technique that allows the study of time-dependent fluctuations without some of the approximations used in this section.

3. Numerical results for nanoscale field-effect transistors

The numerical results presented in this work are computed using a Monte Carlo (quantum) simulator that introduces some features that allow solving a many-electron scenario within 3D and 1D systems. First, we present a brief description of the device under study and the numerical algorithm behind our simulations. Finally we present DC current and noise results for analog and digital applications.

3.1. Device description

We assume that electron transport (from source to drain) takes place along a silicon (100) oriented channel, at room temperature (see figure 3). A double-gate (DG) geometry for the transistor has been considered for numerical simulations, but the qualitative conclusions can be extended to other gate geometries. We assume that electrons can reach the six equivalent ellipsoidal constant energy valleys of the silicon band structure. The effective masses of the ellipsoid are m_l* = 0.9163 m₀ and m_t* = 0.1905 m₀ with m₀ the free electron mass. For details on the particular effective mass value taken by the electrons in each direction and valley see [4]. We consider two different geometries to be able to deal with a 3D bulk and a 1D quantum wire, by controlling the electron confinement. When W and T are much larger than the electron de Broglie wavelength, the active region is a three-dimensional (3D) system (bulk) and there is no restriction on the possible values of the energies of an electron in each of the six valleys. The total electron energy for a particular valley is $E=E_x+E_\perp$ , where the energies E_x and $E_{ \perp }$ are defined as $E_x=\hbar^2k_y / ({2m_t })$ and $E_\perp=\hbar^2k_y / ({2m_t })+\hbar^2k_z / ({2m_l })$ . On the other hand, when T and W are both small enough, the active region becomes a 1D system (a quantum wire) and the energy of an electron in one particular valley is $E=\hbar^2k_x / ({2m_t })+ E_{\mathrm {1D}}^q$ , where $E_{\mathrm {1D}}^q=\hbar^2\pi^2 / ({2m_t L_y^2})+\hbar^2\pi ^2 / ({2m_l L_z^2})$ represents the minimum energy of the first sub-band, whose value is E_1D^q = 0.182 eV for T = 2 nm and W = 5 nm. The energies of the next lowest sub-bands are inaccessible for electrons (E_1D^q = 0.418 eV or E_1D^q = 0.489 eV) and only two valleys become relevant. For the quantum wire, the electron velocities in the z and y directions are zero due to the electron confinement^Note1. Let us notice that we refer to a 3D (bulk) or 1D (quantum wire) system to emphasize the energy confinement in the active region that determines the available energies for electrons. However, the paths of the electrons are defined in the x, y, z directions and, consequently, the electrostatics are obtained through a 3D Poisson solver for all simulations (even for the 1D quantum wire).

Figure 3. Schematic representation of a DG-FET. Electron transport from source to drain takes place along the x direction. The channel (open system) of the FET has arbitrary lateral dimensions, W and T, determining electron confinement.

3.2. Numerical Monte Carlo simulation algorithm

Our numerical algorithm for solving the dynamics of an ensemble of interacting electrons is quite close, but not identical, to the standard Monte Carlo method applied to semiconductor electron devices. This technique is a powerful method for solving the Boltzmann transport equation, which is developed under the mean-field approximation. In the latter, a unique Poisson equation is solved at each time step of the simulation, while in our many-electron Monte Carlo approach we solve N(t) Poisson equations with N(t) different boundary conditions and charge densities. We use a 3D Poisson solver based on a finite-difference scheme. We divide the whole volume Ω of the scenario drawn in figure 3 into Nx Ny Nz cells. Each 3D cell has spatial dimensions DX, DY and DZ. Thus, the active region of our simulating device has a volume equal to (Nx DX)(Ny DY)(Nz DZ) = LWT. The most time-consuming algorithm is that for the solution of the Poisson equation. Therefore, in our algorithm, the simulation time is proportional to N(t) Nx Ny Nz, while it reduces to Nx Ny Nz under standard Monte Carlo simulations. As an example, for a total number of cells, Nx Ny Nz, on the order of 1000–2000 cells and a number of electrons, N(t), of ~ 20–50, the computational time is about 2–3 h for each bias point using a state-of-the-art workstation^Note2.

At the same time, our numerical algorithm includes electron confinement in the active region. Considering the Bohm trajectory modeling of quantum mechanics, it can be demonstrated that the study of electron transport for confinement conditions can be hugely simplified if only one relevant energy level is meaningful in the confined directions [8] (see Note1). In this work we take advantage of this fact by taking into account the same result for the classical Monte Carlo trajectories.

We also use an injection model applicable to systems with arbitrary electron confinement, which is a time-dependent version of the Landauer boundary conditions, valid for degenerate and non-degenerate systems. We inject electrons according to the Fermi–Dirac statistic defined by a Fermi level deep inside the contacts [9, 10]. The applied bias provides a difference between the values of the Fermi level at each injecting surface. Our injection model, coupled to the boundary conditions of the Poisson equation, also assures charge neutrality at the contacts [10].

Finally, as mentioned in the introduction, phonon, impurity, and roughness scattering mechanisms are not taken into account, and only the full (long and short range) Coulomb interaction is considered explicitly. In our algorithm, randomness appears in the rate and properties of the electron injection from the contacts into the volume Ω.

3.3. DC results

In the present section we compute the time evolution of many interacting electrons inside 3D and 1D DG-FETs with the characteristics defined in table 1. The DG-FETs are surrounded by air and metal at the boundary surfaces.

Table 1. Parameters for the DG-FET depicted in figure 3.

	Magnitude	3D bulk	1D Quantum wire
Channel dimensions (nm)	L	30	15
	W	10	5
	T	8	2
	t_ox	2	2
Spatial step (nm)	DX	3	3
	DY	2.5	1.6
	DZ	2	1
Doping (cm^–3)	Channel	1 × 10¹⁰	1 × 10¹⁰
Doping (cm^–3)	Contact	2 × 10¹⁹	2 × 10¹⁹
Simulation time (s)	T	3 × 10^–10	5 × 10^–10
Temporal step (s)	Dt	2 × 10^–16	2 × 10^–16

Figures 4 and 5 present the average values for current at different gate and drain voltages for 1D and 3D configurations. V_GS represents the saturation gate–source bias and V_DS the saturation source–drain bias. The linear region is enclosed below a source–drain bias of 0.1 V while the saturation region is found beyond 0.3 V approximately. On the other hand, saturation gate–source biases are reached around 0.5 V. There, the saturation currents differ between the two configurations. The highest source–drain current is achieved by the 3D configuration, while the lowest is achieved by the 1D system.

Figure 4. Average current for the 1D DG-FET.

Figure 5. Average current for the 3D DG-MOSFET.

3.4. Analog noise results

As mentioned earlier in section 2.1, differences between confined and non-confined systems are expected. Figure 6 indicates these important differences for 3D and 1D FETs. For our 1D system, the Fano factor is bigger than that of the 3D system and the average current is smaller than the 3D one. Therefore, from expression (14) with a bandwidth B = 1 MHz, the 1D S/N ratio is approximately one order of magnitude smaller than the 3D S/N ratio (see figure 7). Hence, the qualitative behavior of the S/N ratio discussed in terms of equation (14) is confirmed numerically by these Monte Carlo results: smaller FETs offer substantially worse analog noise performances than bigger ones.

Figure 6. Average current (solid), I, and Fano factor (dashed) as a function of gate voltage for the three double-gate FET geometries mentioned in the text. The oxide thickness is 2 nm. The drain–source voltage is 0.5 V.

Figure 7. Signal-to-noise ratio for the bulk DG-FET and the quantum wire DG-FET considered here.

3.5. Digital noise results

For digital applications (an inverter), a bit error appears when an input voltage `0' or `1' leads to an erroneous interpretation of the output voltage, because of noise. Here we are wondering about those errors due to intrinsic noise fluctuations. In figures 8 and 9 the probability density for finding certain drain voltages when 0 V is expected is computed for the 1D and 3D systems respectively. Results for two different clock frequencies are presented: 50 and 500 GHz.

Figure 8. Monte Carlo results for the probability density for finding different drain voltages at 50 and 500 GHz for the 1D system.

Figure 9. Monte Carlo results for the probability density for finding different drain voltages at 50 and 500 GHz for the 3D system.

On one hand, the clock frequency plays a key role in the BER. As the clock frequency grows, the faster voltage fluctuations are less and less averaged (see the explanation linked to equation (21)). Therefore, the probability of finding higher drain voltages increases with faster switching.

On the other hand, since the voltage fluctuations are directly related to the capacitance value C (see figure 2), different results are obtained for 1D (C = 1.26 × 10^–18 F), and 3D (C = 5.05 × 10^–18 F) systems. From figures 8 and 9, the corresponding system variance is increased from the 3D configuration to the 1D configuration. Again, the 1D system presents a poorer noise performance behavior. Thus, increasing miniaturization of the FET dimensions implies an important drawback for digital applications, mainly due to a decrease of the associated gate capacitance.

It is worth pointing out that both shrinking dimensions and increasing clock frequencies, two of the principal targets of the ITRS roadmap [1], imply an important increase of the BER due to intrinsic noise.

4. Conclusions

In this work, we have discussed the noise performance of aggressively scaled FETs (with and without confinement) in digital and analog applications. First, the noise performance for analog applications was discussed in terms of the signal-to-noise ratio. Smaller devices produce a smaller average current and a larger Fano factor, leading to a signal-to-noise (S/N) degradation. Second, the performance for digital applications was analyzed in terms of the bit error probability. Incrementation of the clock frequency and reduction of the FET lateral dimensions result in a drastic incrementation of the BER, mainly because smaller devices (with smaller capacitances) are more sensitive to electrostatics. Our results are supported by analytical estimations and numerical results obtained with a powerful Monte Carlo (quantum) simulator. In summary, our work predicts that smaller FETs are intrinsically noisier. This statement may imply a serious limitation for the continuous shrinking of FET dimensions and increasing of clock speed predicted by the ITRS [1]. In view of these (single-finger-device) results, the consideration of new scaling-related strategies (such as using multi-finger devices) seems mandatory for providing nanoscale devices with acceptable noise performances.

Acknowledgment

This work was partially supported by the Ministerio de Ciencia y Tecnología through project TEC2006-13731-C02/MIC.

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Notes

Note1 The electron velocity is equal to zero in the direction where there is energy confinement. This is a reasonable assumption that can be formally justified, for example using Bohm trajectories, when the probability of presence in that direction does not change with time. The main approximation here is assuming that the time dependence of the wavefunction involves only one quantized energy in the aforementioned direction, $\exp (\rmi E_{\mathrm {1D}}^q t / \hbar)$ , because it assumes that the single-particle wavefunction is separable in the 3D space and that only one sub-band is relevant for electron transport. We define the geometries of the 1D system to support these approximations.