28 Noise in Integrated Circuits - conocimientos.com.ve: Carlos L. Briceño R.

In this age of fast time to market requirements, RF front-end designers are increasingly dependent on Computer Aided Design (CAD) tools for fast and first-time-correct designs. Furthermore, with the existence of different transistor technologies from different foundries, the need for CAD tools becomes even more significant as theoretical design methods may need to differ from one technology to another, or from a technology made by one foundry to another. But effective use of CAD tools can only be possible if combined with a global (circuit-specific) valid design methodology in order to deliver those robust results, and deliver them fast. RF circuit design is similar to any other analog circuit design in that achieving acceptable performance parameters (including requirements and constraints) not only relies on the ability of the designer to strike valuable and convenient trade-offs using design parameters but also on the ability of the designer to extract the full potential of the available components in achieving the needed performance..

A review of the design approaches behind some of the recently realised and reported CMOS low noise amplifiers meeting challenging performance requirements reveals that these design approaches lack accurate, flexible and informative simultaneous analysis of performance requirements. The optimal design methodology is one that would simultaneously consider all performance requirements against all design parameters. But as the number of circuit components and/or the number of required performance parameters increase, this becomes increasingly difficult to attain. The latter is the case with the target design of this work which requires an amplifier based on the popular Common Source Common Gate Cascode architecture to achieve acceptable performance when operating as both a Low Noise Amplifier (LNA) and a Power Amplifier (PA) for the relatively low power ZigBee (IEEE 802.15.4) front-end.

Instead, increasing knowledge of how circuit components operate and the significance of the influence certain design parameters have on certain performance parameters can facilitate a design approach where effective early eliminations can be made leading to as many performance parameters as possible being considered simultaneously against a limited number of design parameters.

The design methodology proposed for this LNA/PA design is built around this course of action. The representation is based on visual observation, in 3D graphs, of how performance parameters vary with related design parameters taking into account the multiple dependencies of performance parameters on design parameters. Components are simulated between their minimum and maximum values to explore their full potential and uncover areas of their operation where better results may be obtained. After some initial eliminations and considerations, most of the performance parameters are simulated with respect to the remaining design parameters. This allows the designer to simultaneously analyze the effect of these design parameters on all those performance parameters and hence make satisfactory trade-off decisions. This also gives the designer the ability to reuse the results of this analysis and change trade-off choices if another design with different constraints is needed. The design procedure is also based on simultaneously optimising the two stages of the cascode architecture, reducing the need for iterations in later stages of the design flow.

Optimisation of the Core Circuit Components

The core amplifier circuit (i.e. excluding the matching) to be optimised in this work is shown in Figure 1. It includes the two cascode transistors, the degeneration inductance, and the load inductance.

The optimisation procedures are developed bearing in mind that the inductors in the cascode architecture will only insignificantly affect the DC characteristics of the amplifier due to their relatively small internal resistances. Therefore, the DC analysis can safely be done on the two cascode transistors only without including the inductors, and the results will still be valid when inductors are added. Also, although the effect of these inductors on RF performance is well understood, tests show that in the cascode architecture, a compromised configuration (bias point and device width) for the cascode transistors produced from analysis of the circuit conducted without the inductors cannot be different than if the analysis was undertaken with the existence of the inductors, and hence the transistors cannot have a better configuration.. In other words, although including the inductors will change the resulting circuit performance, if the optimisation (without the inductors) to select a suitable configuration for the two cascode transistors was performed with the inductors in place, then the chosen configuration for the transistors (based on the same judgement procedures) would have been the same. However, it is important to emphasise that this assertion is only valid for the Cascode LNA architecture due to the limited range of values of inductors that are commonly considered for use as either a degeneration inductance in the source of the CS stage or as a load inductance in the drain of the CG stage. Analogy can be made between this and operating on a small section of a nonlinear curve where the small section can be considered linear.

With appreciation of the above assertion, the first step in optimising circuit components is to tune the sizes and biases of the two cascode transistors; this is done on the circuit in Figure 1. This is the simple cascode architecture without the inductive degeneration.

The general approach is to examine all the low and high-power performance parameters concerned against a sweep of sizes of the CS and CG transistors, after appropriately setting the bias voltages at the gates of each stage.

In Figure 1, the gate of the common-gate transistor is connected to the amplifier's . It has been shown in [1] that the third-order input intercept point (IIP₃) of the second stage can be enhanced by increasing V_GS2. But V_GS of transistor M2 is also determined by the voltage between the two stages, hereafter called the "mid-voltage", which is affected by V_DD (the bias voltage on the drain of M2 and the sizes of both transistors, and it can affect current consumption even though this is predominantly controlled by the common-source stage. Hence, to increase flexibility and reduce the scope of possibilities, the gate of M2 is assigned a maximum voltage by connecting it to V_DD. This does not constitute a constraint on V_GS2 since full control over it will still be available through controlling the sizes of both transistors, as will be demonstrated in the DC analysis. The bias voltage of the CS transistor is adjusted with respect to its noise performance. The RF choke placed on the drain of the CG transistor isolates the supply voltage from the amplifier RF output, and keeps the amplifier independent, for now, of any specific load impedance for the purpose of optimisation. The comprehensive DC analysis undertaken investigates the nature of variations of the DC current and the mid-voltage subject to varying transistor sizes.

The noise performance of the cascode architecture is investigated with emphasis on the bias and size of the CS transistor as the dominant contributor to noise in the amplifier. The most suitable CS gate voltage produced from this analysis will be used as a fixed value for the rest of the optimisation process. This does not imply any limit or constraint on any other performance parameters since the current of the CS transistor, which controls the current of the circuit, is equally dependant on its gate voltage and size in the simulated range.

Power, gain and nonlinear analysis are performed by investigating the effect of varying the sizes of the CS and CG transistors on several performance parameters at low and high input powers.

The second step in setting the core circuit components is to include the degeneration inductance and study its effect on both the low power and high power operation. The degeneration inductance affects low power operation in terms of noise for the LNA functionality and affects the nonlinear performance since it is classified as a negative feedback element.

The final step in setting the core circuit parameters is performed by tuning the load inductor. This step is carried out after the transistor sizes and the degenerating inductor have been chosen. The load inductor has a considerable effect on two performance parameters; power gain and stability. The stability of the final amplifier circuit will depend on the impedances presented to the amplifier at the input and the output. In the best case, the core amplifier circuit (before matching) should present unconditional stability. This gives the designer more flexibility in matching the circuit for other performance parameters such as noise, gain and harmonic termination. However, trying to peruse this goal at the beginning of the design flow will significantly complicate the design process, add to design time and may result in unnecessary constraints on other desired performance parameters. Instead, this step is left as the last step in the design of the core amplifier, and the value of the inductor can be decided as a simple trade-off of how it affects stability and gain only.

Employing Linearisation

Two low power linearisation techniques, linearisation by multi-gating and linearisation by harmonic termination are employed in this design.

The auxiliary transistors for multi-gate linearisation cannot be added before deciding the final sizes and biases of the core transistors. The reason for this is that since the bias and width of the auxiliary transistors are tuned to cancel the g₃ nonlinearity of the main transistor, their configuration will not be effective if the configuration of the main transistor changed. If this step is performed as the size of the CS transistor is being swept for optimisation, it might give a better early indication on the nature of the expected nonlinear performance. But this would involve too many iterations as the configuration of the auxiliary transistors would have to be changed every time the CS transistor configuration is changed; hugely increasing design time. It is also not possible to write a mathematical routine in the simulator to automatically re-adjust the sizes and biases of the auxiliary transistors for g₃ cancellation whenever the core transistor is changed. This is because an exponential exists in the equation describing the relationship between the 3^rd-order transconductance nonlinearity of a common-source transistor in moderate inversion with its dimensions and bias [2].

In the light of this, a better approach for optimising the auxiliary transistors is to choose the width of the core transistors based on the various amplifier performance parameters (such as noise, gain, PAE, etc.) and then linearize that by multi-gate transistor (MGTR). Since it does not significantly affect the DC current in the cascode, adding the auxiliary transistors will not affect any other performance parameters set by optimising the main transistor, but will only improve its linearity.

The linearisation by MGTR method will still be valid at the relatively high power for PA operation because although the instantaneous g_m will change with higher powers, the average g_m (around the DC bias) will remain the same.

The harmonic termination is incorporated within the source- and load-pull analysis which is extensively extended (by increasing the number of simulated-for impedances) to take into account all possible terminations. The effect of any impedance representing considerable termination to any frequency component which contributes to the third-order intermodulation distortion (IMD₃) will be reflected in the input or output contours and can then be picked by the designer for matching.

Matching the Amplifier

In the proposed design methodology, matching the amplifier comes as the last step after setting the core circuit parameters and applying linearisation; this is because these two processes contribute to the impedances seen at the input and the output of the amplifier core circuit. In high power operation, small signal matching techniques are no longer valid; because they are primarily based on S-parameters which is essentially a small signal-only analysis. For example, the load of the amplifier cannot be matched for maximum power transfer with the conjugate matching requirements obtained from S-parameter measurements when the amplifier is operating at its 1dB compression point which is a large-signal operating condition. Instead, source and load pull simulations must to be performed. Source and load pull simulations consider a number of different matching impedances spread across the Smith chart (pre-specified by the designer) and investigates the response of the circuit in terms of obtainable performance parameters when these impedances are presented to the input and the output of the core amplifier circuit, respectively.

The matching of the amplifier could be investigated by simultaneously considering low and high power matching techniques, giving the designer the flexibility of selecting the desired trade-off.

References

[1] Zhenying, L., Rustagi, S. C., Li, M. F. and Lian, Y., "A 1V, 2.4GHz fully integrated LNA using 0.18µm CMOS technology," In Proceedings of IEEE 5th International Conference on ASIC, vol.2, pp.1062-5, (2003).

[2] Toole, B., Plett, C. and Cloutier, M., "RF Circuit Implications of Moderate Inversion Enhanced Linear Region in MOSFETs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol.51 (2), pp.319-328, (2004).

Nombre: Carlos L. Briceño R.

Materia: Comunicaciones de RF

Fuente: http://mwexpert.typepad.com/home/2009/06/index.html