For ease of presentation, in this paper our discussion will be focused on one type of dynamic circuits known as domino CMOS logic circuits [3], which is probably the most widely used dynamic logic style. However, it is noted that the noisetolerant design techniques discussed in this paper can also be applied to other types of dynamic circuits. A typical n-type domino CMOS logic gate, as shown in Fig. (a), onsists of clock controlled transistors M1 and M2, a pull-down n-type transistor network, and an output driver. He operation of a domino CMOS logic gate can be divided into two phases. In the precharge phase when the clock CK is low, the dynamic node S is charged to logic high through M1 and the output of the gate Q is low. The evaluation phase starts when the clock goes high. In this phase, M1 is OFF and M2 is ON. The dynamic node S discharges or retains its charge depending on the inputs to the pull-down network. An example 2-input domino AND gate is illustrated in Fig. (b). Noise sources in dynamic logic circuits can be broadly classified into two basic types: i) gate internal noises, including charge sharing noise, leakage noise, and so on and ii) external noises, including input noise, power and ground noise, and substrate noise.
1) Charge sharing noise is caused by charge redistribution between the dynamic node and the internal nodes of the pull-down network. Charge sharing reduces the voltage level at the dynamic node causing potential false switching of a dynamic logic gate.
2) Leakage noise refers to the possible charge loss in the evaluation phase due to subthreshold leakage current. Leakage current increases exponentially with respect to transistor threshold voltage, which is continuously being down-scaled as the power-supply voltage reduces. Therefore, leakage in transistors can be a significant source of noise in wide dynamic logic gates designed using very deep submicron process technology.
3) Input noise refers to noise presented at the inputs of a logic gate. They are primarily caused by the coupling effect, also known as crosstalk, among adjacent signal wires. This type of noise has become a prominent source of failures for deep submicron VLSI circuits because of the aggressive interconnect scaling in the lateral dimensions with relatively unchanged vertical dimensions.
The simple feedback keeper technique is effective against noises and is easy to design. However, there is a fundamental dilemma in choosing the size of the keeper. On one hand, a strong keeper is required to achieve high gate noise tolerance. On the other hand, large keeper leads to significant contention during normal gate switching, therefore deteriorates gate performance. The conditional keeper techniques temporarily disable the keeper or reduce keeper strength to alleviate the contention problem. But dynamic gates equipped with those keepers are susceptible to input noise glitches because the dynamic node is not adequately protected during the gate switching time window. Noise immunity against input noises is very difficult to achieve without significant sacrifice in circuit performance because the gate should not act before it identifies whether the input is noise or real signal. This inevitable time needed to distinguish noise from real signal, which is obtained by monitoring the initial period of the input voltage waveform, causes degradation in circuit performance. The performance overhead due to the additional circuitry that helps improve input noise immunity cannot be completely eliminated. However, it can be reduced to a large extent. In this paper, we propose a new technique that enhances dynamic gate noise immunity against all types of noises including the input noise. The proposed technique incurs very little cost in performance.
NOISE MARGIN AND DELAY ANALYSIS
In this section, we analytically study the noise margin as well as the discharge time of domino logic gates with the proposed NDR keepers. For simplicity of analysis, we assume the – characteristic of the NDR keeper can be modeled using a piecewise linear waveform as shown in Fig. (a), where is the peak current, is the peak voltage, and is the voltage when the current first becomes negligible. The input signal is assumed to have a saturated ramp waveform with a rise time of . To facilitate manual analysis, we have further assumed this ramp input can be approximated by a step waveform, as shown in Fig. (b), where the sizes of the shadowed areas are matched.
Diego A. Cáceres M. C.I 19235570 Materia: CRF
No hay comentarios:
Publicar un comentario